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| AN45 DESIGN GUIDE Introduction The ProSLIC(R) from Silicon Laboratories integrates a complete analog telephone interface into one low-voltage CMOS device and offers extensive software programmability to meet many global telephony requirements and customer specifications. In addition to performing all BORSCHT functions, the Si321x also dynamically generates and controls its own battery voltage, eliminating the need for external battery supplies. Two different battery generation architectures are supported: a BJT/inductor design offering a low-cost battery supply solution, and a MOSFET/transformer design offering increased power efficiency and a wider range of input voltages. This application note gives specific guidance in determining dc-dc converter power requirements and selecting component values for each of the dc-dc converter architectures. FOR THE Si3210/15/16 DC-DC CONVERTER Si321x DC-DC Converter Description The dc-dc converter dynamically generates the large negative voltages required to operate the linefeed interface. The Si321x acts as the controller for a buck-boost dc-dc converter that converts a positive dc voltage into the desired negative battery voltage. In addition to eliminating external power supplies, this allows the Si321x to minimize power dissipation by dynamically controlling the battery voltage to the minimum required for any given mode of operation. Input + VDC - Output + DC-DC Converter VBAT - TIP + VTR - Twisted Pair Line RLINE 2 Telephone Hook SW. RLINE 2 Ringer RDC RING Linefeed Circuitry Figure 1. Linefeed Power Diagram Power Output Requirement Understanding the maximum power required by the ProSLIC linefeed circuitry to operate a worst-case specified load is the first step in determining the dc-dc converter design solution. Figure 1 defines the linefeed circuit and load circuit in basic blocks of circuitry. Typically, the ringing state is the highest power consumption state for the SLIC, but in special cases the off-hook state can have the highest. Guidance in calculating each of these states is offered in this section. The ringer impedance of one telephone is defined as an 8 F cap in series with a 6930 resistor. This is approximately the same impedance as 7000 at 20 Hz and is defined as 1 REN (ringing equivalence number). Since there can be N number of telephones connected Rev. 0.5 7/03 in parallel to the TIP and RING lines, the equivalent impedance of the parallel ringers can be computed as the following (NREN is limited to 1 to 5): 7000 R NREN = ----------------NREN During ringing, the TIP-to-RING peak voltage, VTR_PK, is the sum of the rms voltage drop across the ringer circuit, VRINGrms, the line resistance, and the internal source resistance of 160 . V RINGrms x 2 7000 V TR_PK = -------------------------------------- x ----------------- + R LINE + R s 7000 NREN NREN Copyright (c) 2003 by Silicon Laboratories AN45-050 AN45 Considering the resistance of 26 gauge telephone wire, which is 0.45 per feet, this equation becomes the following: V TR_PK V RINGrms x 2 7000 = -------------------------------------- x ----------------- + 2 x Dist x 0.045 + 160 7000 NREN NREN 0.6 V + 80 ( I LIM + I BJTBIAS ) I BAT = I LIM + I BJTBIAS + ----------------------------------------------------------------------- 5100 Equation 5 where ILIM is the current limit set by Register 71, and IBJTBIAS is the bipolar biasing current set by the direct Register 65. There are two power equations for different track settings. For TRACK = 1, VBAT is allowed to track the line resistance to minimize power consumption. The power equation for this mode is as follows: P OFFHOOK = I BAT ( V CM + V OV + I LIM x R LOOPMAX ) Equation 1 The required VBAT is equal to VTR_PK plus VCMR, which is the voltage drop across the linefeed circuit. The VCMR voltage is set by the indirect Register 40 and recommended to be 1.5 V for most applications. V BAT = V TR_PK + VCMR Equation 6 Equation 2 The worst-case peak current for NREN load is when the load is connected with a short loop of negligible line resistance. V TR_PK I PK = --------------------------------------( 7000 NREN ) where VCM is set by the direct Register 73, and VOV is set by Register 66. RLOOPMAX is the maximum total loop resistance (RLINE + Phone's RDC + RS) where RS is the internal series resistance. For TRACK = 0, VBAT can ramp up quickly to support the brief on-hook voltage measurement feature, the power equation is as follows: P OFFHOOK = I BAT x V BATL Equation 7 where VBATL is set by the direct Register 75. If the off-hook power consumption is greater than the power during ringing, the dc-dc converter should be designed based on the off-hook current and off-hook VBAT. However, the requirement for the switching components (Q7 and Q8 or M1) should still be based on the VBAT value during ringing. This yields an average current equation: I AVG 2 x NREN x V TR_PK 2 = I PK x -- = ----------------------------------------------------7000 Equation 3 The total output power required during ringing is equal to the power consumed in the load plus the power consumed in the sensing resistors and the external transistors of the linefeed circuitry. This leakage current has a magnitude of 2.5 mA. P OUT = V BAT x ( I AVG + 0.0025 ) Power Input Requirement The input power is equal to the output power plus the wasted power during the power conversion process. The efficiency of the Si321x dc-dc converter is mainly dependent on the inductor loss (copper and magnetic loss) and the switching loss. For worst-case estimation, the efficiency is assumed to be 60% for the BJT/inductor solution (the actual efficiency is between 63% and 73%) and 75% for the MOSFET/transformer solution (the actual efficiency is between 75% and 83%.) P O = P IN x Power Efficiency = I IN x V IN x Power Efficiency Equation 4 In the Off-Hook State In a few special cases, the power consumed during off-hook is higher than the power consumed during ringing. It is important to check for this and design the power supply to handle the larger power requirement. Most designers can skip this section unless their designs support long line and/or the brief on-hook voltage measurement (for caller ID 2 and 2.5) with TRACK = 0 (bit 0 of the direct Register 66). The output current equations in the off-hook active state are as follows: Solving for IIN: PO I IN = ---------------------------------------------------------------( V IN x Power Efficiency ) Equation 8 The input voltage to the dc-dc converter could drop quickly (depending on the source impedance) as the 2 Rev. 0.5 AN45 input current rises. The VIN minimum is defined as the input voltage level at the maximum input current defined in Equation 8. It is important that the VIN minimum is used as the VDC in the design calculation to prevent the dc-dc converter from receding below the low-voltage lock-out threshold, which could cause the dc-dc converter to shut down prematurely. Solution The typical circuit application for the BJT/inductor version of the Si321x dc-dc converter is shown in Figure 2. Components in this circuit are discussed, and detailed descriptions for each functional block are provided to guide the designer through the component value selection process. Component Selection for BJT/Inductor +VDC Fuse DCMONH R19 RMONH C25 10 C14 0.1 DCMONL R20 RMONL C10 CFF R16 RSW R18 RVDC DCFF DCDRV .1 mF Q8 Q7 QBATD FZT955 D1 DSW ES1D R21 RFILT C9 CBAT 10 C26 CFILT VBAT 2222 QBATD Q9 2222 VCC R28* R17 RSWE L1 LSW R29* VBAT Figure 2. Typical Application Circuit Power Inductor Design Equation The L1 inductor is the main power component in the Si321x dc-dc converter. Energy from the input is stored into the L1 during Q7 switch transistor on-time and released to the output during Q7 off-time. The amount of this energy is directly proportional to the inductance of the inductor and to the square of the maximum current that flows through the inductor during on-time. L x I MAX E = -----------------------2 2 L x I MAX x Fs L x I MAX E P IND = --- = ------------------------ = ------------------------------------2T 2 T 2 2 where Fs is the switching frequency of the Q7 transistor. This frequency represents the number of times that the energy transfers from the input to the output via the inductor per second. The output power can be related to inductor power with the efficiency factor, which is defined as the ratio of the output power over the input power. L x IMAX x Fs P OUT = E FF x P IND = E FF ------------------------------------- 2 2 The inductor power equation is derived as the energy over time: Equation 9 Rev. 0.5 3 AN45 In the Discontinuous Switching mode, the current flowing in the inductor always starts at 0 A at the beginning of on-time of Q7, peaks at the end of the on-time, and goes back to zero at the end of off-time. During on-time, VDC is presented across the L1 inductor and the current flow increases linearly (see Figure 3) with respect to the on-time duration of Q7. The rate of the current increase depends on VDC and the inductance of L1. V DC i ( t ) = ---------- x t L current. This increase in the inductor current raises storage energy in L1; Therefore, more energy is available to the output when Q7 is off. The inductor current reaches its peak IPK at tONMAX. V DC I PK = ---------- x t ONMAX L So, the maximum on-time is as follows: I PK x L t ONMAX = ----------------V DC As the output demands more energy, the Si321x lengthens Q7 on-time to increase the L1 inductor The off-time equivalent circuit is shown in Figure 4. Q7 is off and the inductor current follows the diode, D1, to the C9 output capacitor and the RLOAD. Q7 SW + I PK V DC Slope = di/dt = V DC /L i(t) L1 - t O NM AX Figure 3. L1 Current Flow during Q7 On-Time D1 - I PK L1 Slope = di/dt = V BAT /L IL - - C9 + R LO AD V BAT + t O FFM AX + Figure 4. L1 Current Flow during Q7 Off-Time 4 Rev. 0.5 AN45 The voltage across the inductor during this time is equal to VBAT less the D1 diode voltage drop or approximately VBAT. Since VBAT is greater than VDC, the rate of current change is faster compared to the current slope during on-time. The inductor current starts from IPK and descends to 0 A at tOFFMAX. V BAT I PK ---------------------- = ------------t OFFMAX L 2. Calculate the inductance, L, based on Equation 13 assuming worst case 60% efficiency. Since inductors tend to have tolerances in the range of 5% to 30%, the minimum value of inductance must be equal to the calculated value of the inductor. Vary Fs from 64 kHz to 128 kHz to obtain the desired inductance value. 3. Calculate the period, T, for Fs and the corresponding value for direct Register 92 in hexadecimal. TPWM Period Register 92 = -------------61 ns So the maximum off-time is as follows: I PK x L t OFFMAX = ----------------V BAT Equation 14 4. Calculate the maximum off-time and the corresponding value for direct Register 93 in hexadecimal. ( I PK x L ) V BAT t OFFMAX Direct Register 93 = ---------------------- = ---------------------------------------61 ns 61 ns Equation 10 The period of the switching frequency, Fs, is equal to the reciprocal of the maximum on-time plus maximum off-time: 1 1 Fs = ------------------------------------------------- = --------------------------------------------------------------------------I PK x L V DC + I PK x L V BAT t ONMAX + t OFFMAX Equation 15 Selecting a DC-DC Converter Switching Transistor The switching transistor (Q7) on the typical application circuit is shown in Figure 2 on page 3. This transistor is turned on by the base drive current through Q8 while R16 provides the discharge current path for Q7's base-emitter capacitor during turn-off. The capacitor, C10, provides additional charge pump boost current from the DCFF pin of the Si321x to turn Q7 off faster. C10 with a value of 22 nF is sufficient for most applications. R16 plays an important role in turning off the Q7 transistor, but R16 also robs the Q7 base drive current during the on-time. With a value of 200 , R16 does an adequate job of turning Q7 off and only takes 3 mA from the base current during on-time. 0.6 R16 = ---------I R16 Substituting the above expression for the power Equation 8: L x I PK x Fs P OUT = E FF x P IND = E FF --------------------------------- 2 2 Equation 11 And solving for IPK: 2P OUT ( V BAT + V DC ) I PK = -----------------------------------------------------E FF x V BAT x V DC Equation 12 Solving for L from Equation 11, the required inductance is expressed as: 2P OUT L = ---------------------------------------E FF x I PK 2 x Fs Equation 16 Table 1 lists the requirements for the switching transistor, Q7. Equation 13 The optimum switching frequency of the Si321x dc-dc converter is between 64 kHz and 85 kHz. Faster switching frequency is generally less efficient. This is a common characteristic of the PNP switching element and low-cost inductor magnetic material. Power Inductor Selection Once output power (POUT), VDC, and VBAT are clearly defined, the inductor can be selected as follows: 1. Calculate IPK based on Equation 12 (assumed 60% efficiency). This is the maximum current requirement for the inductor. Table 1. Switching Transistor Q7 VCEO > |VBAT| + VDC VEBO > VCC VCBO > |VBAT| + VCC + VDC ICMAX > IPK (maximum Inductor current) fT > 100 MHz Another critical specification is the transistor gain at ICMAX. The higher the transistor gain (hFE), the less base current is required to keep it in saturation during Rev. 0.5 5 AN45 on-time and the more efficient the converter will be since the base current is not delivered to the load. Also, as more base current is required, it becomes more difficult for the DCDRV and DCFF pins to switch the transistor off quickly, which further decreases efficiency. Practically, Q7 gain should be around 100 at peak inductor current. Si321x Bipolar Switch Driver In Figure 2, the Q8 collector current provides the base current drive that turns the switch transistor Q7 on. The base current drive should be sufficient to keep Q7 in saturation at IPK. The overdrive factor of 1.3 is sufficient. I CMAX --------------- < h FEmin@ICmax I BQ7 I CMAX I BQ7 = 1.3 x ------------------------------------h FEmin@ICmax time constant of less than 100 s to maintain loop stability. See CFILT and RFILT in Figure 2. (Recommended values for these two components are .1 F and 15 , respectively.) Undervoltage and Overcurrent Protection The Si321x dc-dc converter is designed to operate under a specific input voltage and output loading condition. When the input voltage goes too low, there is not enough power from the input to deliver to the output; so, the dc-dc converter may try to draw excessive current in an attempt to deliver power to the output. A similar condition exists when the output ramps up too fast (during power up, transient loading), short loads, or unintentionally overloads the output. To prevent damage to the switching transistor during these abnormal conditions, the Si321x implements an undervoltage and overcurrent mechanism. VDC Pin 8 R19 Equation 17 The Si321x sets the DCDRV pin high to create the base current drive through Q8. The values of R17 and VCC control the base drive current. I BQ7 V CC - 0.6 V 0.6 V = ------------------------------- - ------------R 17 R 16 4.5 k SDCH 0.8 V DC Si3210 R18 V CC - 0.7 V R 17 = --------------------------------------------I BQ7 + 0.6 V R 16 Equation 18 4.5 k Pin 9 SDCL 0.8 V DC R20 IC Transistor requirements for Q8: VCEO > VCC + VDC VEBO > VCC VCBO > VCC + VDC fT > 200 MHz Selecting Output Capacitor and Filter The output capacitor, C9, is subject to large ac currents from the inductor and should have low equivalent series resistance (ESR) to minimize ripple voltage on VBAT. V RIPPLE = ERS MAX x I PK Q7 Figure 5. Protection Sense Circuitry Undervoltage Lock-Out The undervoltage lock-out is implemented via the SDCH pin as shown in Figure 5. When the VDC goes under a specified value, the current flow through R19 into the SDCH pin goes under 120 A, and it triggers the Si321x to shut off the dc-dc converter. The equation for R19 with a specific VDC is given by the following: VDC ------------ - 0.8 1.5 = --------------------------- - 4.5 k 120 A Equation 19 A 10 F, 100 V electrolytic capacitor provides adequate filtering in most applications. An RC filter between C9 and the load reduces ripple voltage on the VBAT output. This filter should have a 6 R 19 Equation 20 Rev. 0.5 AN45 R19 should be calculated with a 20% lower value in VDC to prevent premature low-voltage lock-out. If the voltage lock-out is activated too often or if the Si321x goes in and out of low-voltage lock-out and creates an oscillation-like condition at the input voltage, it indicates that the input power source has high impedance and should be replaced with a better power source. However, the values of R18, R19, and R20 should be checked against the intended low-voltage lock-out before any conclusion is made about the input power source. Overcurrent Protection Overcurrent protection is implemented via the SDCL pin. (See Figure 5.) The circuit is designed to produce equal current flow from VDC to both the SDCL and SDCH pins with zero current flow through Q7. (R20 is set to be equal to R19 and the value of R18 is small.) When current flows through Q7, it generates a voltage drop across R18 and reduces the current flow into the SDCL pin. When the current flow into the SDCL pin is 10.5 A lower compared to the current flow into the SDCH pin, it triggers the overcurrent protection, and the Si321x ends the current PWM cycle to prevent excessive current flow through Q7. The overload current should be set 20% above the maximum inductor current to prevent current shut down prematurely. 4.5 k + R 19,20 R 18 = 10.5 A x -------------------------------------------1.2 x I OVERLOAD Q9 can be any NPN low voltage (12 V or higher) general-purpose transistor (2N2222 is recommended). The equations for R28 and R29 are as follows: ( VCC + VBE ) R28 = -----------------------------------148 A where VBE = .55 V. V CLAMP R29 = -------------------148 A where VCLAMP is the clamping voltage for VBAT. VCLAMP should be set to a voltage less than the voltage rating of the external components and higher than the maximum VBAT to be generated for a given application. Design Example Suppose that the system requires 5REN of loading on 1680 ft. of line length with a ringing signal 45 V RMS at the phone. The fast voltage measurement feature is not supported, and the system prefers optimization for power saving. The system has regulated 5 V as the main supply voltage for the Si321x and an unregulated 12 V dc with a .75 A current rating. Step 1: Define the Output Requirement Calculate VTR_PK from Equation 1: V RINGrms x 2 7000 V TR_PK = -------------------------------------- x ----------------- + 2 x Dist x 0.045 + 160 7000 NREN NREN Equation 21 A fuse or other power overload circuit should be placed between the VDC power supply and each input of the ProSLIC dc-dc converter circuit (one per ProSLIC solution) to protect the switching components (Q7 or M1) from potential electrical overstress in the event of a hardware fault condition. For more information concerning fuse selection, please contact Silicon Labs. 45 x 2 7000 V TR_PK = ------------------- x ------------ + 2 x 1680 x 045 + 160 = 76.5 7000 5 5 From Equation 2: V BAT = V TR_PK + VCMR = 76.5 + 1.5 = 78 V Output Overvoltage Protection It is possible for the dc-dc converter to generate excessively high voltage beyond the voltage rating of external components. To prevent damage to these components, a transistor (Q9) is added to limit the VBAT to a desired level. Resistors R28 and R29 are connected between VCC and VBAT as a biasing circuit for the transistor, Q9. When VBAT approaches the predetermined voltage level set by R28 and R29, Q9 is turned on and takes current from R20 away from pin SDCL and, consequentially, triggers the Si321x to end its current PWM cycle. From Equation 3: 2 x NREN x V TR_PK 2 I AVG = I PK x -- = ---------------------------------------------------- 7000 2 x 5 x 76.5 I AVG = ------------------------------ = 34.79 mA 7000 The output power equation becomes P OUT = V BAT x ( I AVG + 0.0025 ) = 78 x ( 0.03479 + 0.0025 ) = 2.9 W Rev. 0.5 7 AN45 Step 2: Selecting Output Power Requirement Set up for power optimization in the active off-hook mode: I LIM = 20 mA ( Register 65 ) I BJTBIAS = 4 mA ( Register 66 ) Track = 1 ( Register 71 ) V CM = 3 V ( Register 73 ) V OV = 9 V ( Register 66 ) 2P OUT L = ---------------------------------------- = 100 H E FF x I PK 2 x Fs Fs = 89.5 kHz Step 4: Selecting the Power Inductor Calculate the IPK using Equation 12: 2P OUT ( V BAT + V DC ) I PK = ------------------------------------------------------ = 1.14 A E FF x V BAT x V DC Calculate the L1 Inductance from Equation 13: From Equation 5: I BAT = I LIM + I BJTBIAS + ( 0.6 + 80 ( I LIM + I BJTBIAS ) ) 5100 = 24.5 mA (This frequency was selected to round up the inductor value to 100 H.) 1T = --------------- = 11.2 S 89500 From track 1 Equation 6: P OFFHOOK = I BAT ( V CM + V OV + I LIM x R LINE ) = 24.5 mA ( 3 + 9 + 20 mA ( 2 x 2000 x 0.045 + 160 ) ) = .46 W From Equation 14: 11.2 S Period Register 92 = -------------------- = 183 = b7 H 61 nS From Equation 15: Conclusion: The 2.9 W ringing power is the worst-case power requirement because the active off-hook power requirement is much lower (.46 W). The ringing power is used for the design of the dc-dc converter. Step 3: Define Input Requirement for the 12 V DC From Equation 8: I IN P OUT 2.9 = -------------------------- = -------------------- = 0.4 A V IN x 60% 12 x 0.6 V CEO > V BAT + V DC = 78 + 10 = 88 V V EBO > V CC = 8 V V CBO > V BAT + V CC + V DC = 78 + 5 + 10 = 93 V I CMAX > I PK = 1.14 A Speed: f T > 100 MHz t OFFMAX 0.98 x ( 100 H ) 75 Delay Register 93 = ---------------------- = ----------------------------------------------------61 nS 61 nS = 21 = 15 H Step 5: Selecting the Q7 Switching Transistor Transistor requirement: Experiments with the unregulated 12 V source showed that the actual VDC voltage drops down to 10 V at input current equal to .36 A. The adjusted VDC and IIN is as follows: V DC = 10 V P OUT 2.9 I IN = -------------------------- = -------------------- = 0.48 A V IN x 60% 10 x 0.6 The Zetex FZT955 bipolar transistor meets all of the above requirements and its HFE gain at IPK = 1.14 A is 100. Let IR16 = 3 mA for adequate Q7 base capacitor discharge. From Equation 16: 0.6 R16 = -------------- = 200 0.003 The total current drew on the 12 V unregulated supply is .48 A, which is well within the 12 V unregulated maximum specification of .75 A. 8 Rev. 0.5 AN45 Step 6: Select the Base Drive Circuit Q8 transistor requirement: V CEO = V CC + V DC = 5 + 10 = 15 V V EBO = V CC = 5 V V CBO = V CC + V DC = 5 + 10 = 15 V Speed: f T > 200 MHz Table 2. Component Voltage Rating Components C9, C26, C3, C4, C5, C6 Q1-Q4 (2N5401) Q5, Q6 Q7 Voltage Parameter VC - 1.5 VCEO VCEO Voltage Rating 98.5 150 150 The general purpose 2222 transistor meets all of the above requirements. Calculate the value for R17: Base current drive requirement for Q7 From Equation 17: 1.3 x I MAX 1.3 x 0.98 I BQ7 = -------------------------- = ------------------------- = 12.74 mA H FE 100 VCEO - VDC 100 - 12 = 88 Therefore, VCLAMP must be greater than 78 V but less than 88 V: VCLAMP = 85 V. If VCC = 5 V, then ( 5 + .55 ) V R28 = ---------------------------- = 37.4k 148 A 85 V R29 = ------------------- = 574k 148 A From Equation 18: V CC - 0.6 R17 = ----------------------------------------- = 275 I BQ7 + 0.6 R16 Step 7: Under Voltage Circuit Design Set under voltage lock-out to be 20% lower than the minimum VDC. V UNDER = ( 1-20% )VDC = 8 V MOSFET/Transformer Design DC-DC Converter The MOSFET/transformer dc-dc converter solution offers higher power efficiency than the BJT/inductor solutions and is the preferred solution for applications using low VDC input voltages. The transformer dc-dc converter circuit is shown in Figure 6. R16, R17, Q7, and Q8 are eliminated. The M1 MOSFET is the main power-switching component in this design. The Si321xM version of the ProSLIC is used to directly drive the M1 MOSFET using the DCFF pinout. From Equation 20: V UNDER - 0.8 R19 = ----------------------------------- - 4500 = 56K 120 A R19 = R 20 = 56K Step 8: Overcurrent Protection I OVERLOAD = 1.2 x I MAX = 1.176 A From Equation 21: 10.5 A x ( 4500 + R19 ) R18 = --------------------------------------------------------------- = 0.5 I OVERLOAD Step 9: Output Overvoltage Protection VBAT max = 78 V (during ringing). See Table 2 for voltage ratings. Rev. 0.5 9 AN45 VDC Si3210M SDCH 8 R19 RMONH Fuse R18 RVDC R20 RMONL SDCL 9 T1 1 DCFF DCDRV 33 C27 470pF 34 3 3 M1 2 R23 200k 1 IRLL014N International Rectifier Note 1 4 6 ES1D 10 C9 CBAT 10 uF R22 22 2 D1 DSW Transformer Note 2 C25 10 uF C14 0.1 uF R21 15 VBAT RFILT CFILT C26 0.1 uF Q9 2222 VCC R28* R29* VBAT Figure 6. Transformer DC-DC Converter All relevant design equations for the inductor dc-dc converter are applied in the same manner for the transformer dc-dc converter except for the following equations. Equation 10A During the off interval, the switch current goes to 0 and the primary voltage is the reflection of the VBAT: VP = N VBAT. The transformer mutual primary current equation becomes ! NP N = -----NS NS is the number of turn of the secondary winding. Equation 12A: Deriving the peak current equation based on the new tOFF - MAX 10A equation: 2P OUT x ( N x V BAT x V DC ) I PK = ----------------------------------------------------------------------E FF x N x V BAT x V DC N x V BAT i ( t ) = I PK - ----------------------- ( t ) LM Equation 12A Equation 13A Use the former Equation 13 and solve for FS. 2P OUT F S = -----------------------------------E FF x L x IPK 2 In the discontinuous mode, the current goes to 0 at the end of the off time interval: N x VBAT 0 = I PK - ----------------------- t OFF LM - MAX Equation 13A Switching MOSFET Requirements Due to the low voltage and low current drive capacity of the DCFF pin, logic level MOSFET must be used. Table 3 lists the requirement for the switch MOSFET. Solving for tOFF - MAX: t OFF I PK x L = ----------------------N x V BAT - MAX Equation 10A Where N is the transformer turn ratio: NP is the number of turn of the primary winding. 10 Rev. 0.5 AN45 Table 3. Switch MOSFET M1 VDSS > N x VBAT + VDC ID MAX > 3 x IPK at VGS = 3 V RDS 0n < .2 at ID MAX VGS (th) < 2 V CISS (input cap) < 300 pF COSS (output cap) < 60 pF CRSS (reverse t. cap) < 30 pF Total gate charge: 14 nC tON (VDD = 50 V, ID = 4 A) < 10 ns tOFF (VDD = 50 V, ID = 4 A) < 20 ns Power Transformer A transformer was designed for the Si321x dc-dc converter based on the TDK PC40EF12.6 E core. This transformer has three primary windings connected in series (see Figure 7) to handle all VDC voltage ranging from 3 V to 35 V (consult the factory for higher VDC). The secondary winding can generates up to 94.5 V VBAT at any in range VDC input. Table 4 shows the voltage and the transformer ratio N value for each of the winding connection. Core Material: E core, TDK PC40EF12.6-Z, or equivalent Air Gap: Center leg .088 mm Bobbin: 10 pin (ready for pick and place) Winding: W1-2 = W2-3 = W3-4 =20T, #28 wire W6-10 = 40T, #33 wire Inductance: W1-2 = 11.3 H 10% (only one winding needs to be tested) W1-3 = 45.2 H 10% W1-4 = 107 H 10% MOSFET/Transformer DC-DC Converter Design Procedure The transformer dc-dc converter design procedure is similar to the design of the inductor dc-dc converter. Below are design steps based on the BJT/inductor design example. 1. Step 1 to step 2 are identical to the BJT/inductor dc-dc converter 2. In step 3, use 75% efficiency for input power calculation. 3. In step 4, the peak current is calculated using Equation 12A; the maximum delay time for Register 93 is calculated using Equation 10A; the switching frequency FS and the period for the Register 92 is calculated using Equation 13A. The inductance of inductor L in equations 10A and 13A is selected from Table 4 based on the VDC voltage level. 4. Step 5 now handles the selection of the M1 MOSFET based on the requirements on Table 3. 5. Step 6 is no longer needed since the drive transistor Q8 is eliminated. 6. Steps 7 and 8 are the same. 7. In step 9, use the voltage rating for M1 instead of Q1. The voltage parameter for M1 is as follows: V DSS V = ------------- - VDC N 8. Other components in the circuit that are not discussed above should use the component values recommended in Figure 6. Table 4. Transformer Winding Connection VDC Voltage 3 V to 9 V 10 V to 15 V 16 V to 35 V Winding Connection Winding 1-2 Winding 1-3 Winding 1-4 1 2 3 4 10 Ratio N .2 .4 .6 6 Primary Inductance 11.3 H 45.2 H 107 H Figure 7. Winding Connections 17.7 9.4 2.54 1 10 1.2 5 6 4.17 Com ponent Side Figure 8. Recommended PCB Layout Rev. 0.5 11 AN45 Document Change List Revision 0.4 to Revision 0.5 " " " " Equation 6 ! Changed RLINE to RLOOPMAX. Updated text. Added +160 to first equation. Added +160 to last equation. Changed =.3822 to .46 W. Changed .312 to .46 in last paragraph. "In the Off-Hook State" ! "Step 1: Define the Output Requirement" ! "Step 2: Selecting Output Power Requirement" ! ! ! " " Added SLIC series resistance. VCMR adjustment. " Changed Si3210 to Si321x throughout. 12 Rev. 0.5 AN45 Notes: Rev. 0.5 13 AN45 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 14 Rev. 0.5 |
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